1. Field of the Invention
The present invention is directed to a microcontroller that has an address range for data and instruction memories that includes sixteen megabytes divided into two hundred and fifty six pages of sixty four kilobytes each, and that has a page zero mode which limits program code and data addresses to a first page of instruction and data memory and, more particularly, to a system where all instruction and data addresses are limited to the least sixteen significant bits of a possible twenty four bit address allowing improved performance and reduction in the use of stack space.
2. Description of the Related Art
In microcode program controlled microcontrollers that allow large amounts of instruction and data memory, such as sixteen megabytes, and use a large address, such as twenty-four bits, when a program is limited to a smaller segment of the memory, for example 64 kilobytes (kb), instruction and data address bits 15-23 do not change and instruction clock cycles updating these bits during a fetch (read) or place (write) operation are wasted, resulting in less efficient execution in such situations. When the microcontroller is configured with only a limited amount of instruction and data memory, such as 64 Kb, the same waste of clock cycles can occur. This waste of instruction clock cycles is particularly apparent when jump, call and return and other program flow change type instructions are executed. The waste is even more apparent when interrupts and exceptions and the returns from these operations are performed since the operations move the program counter contents to and from a stack.
What is needed is a system that does not update and ignores the most significant bits of an address during fetch and place or write operations.